About Vennsa

    Vennsa Technologies is the first EDA company dedicated to debugging and error localization. Leveraging over 15 years of research and patented intellectual property from the University of Toronto, Vennsa's technology has been validated by numerous industrial partners. Vennsa is well funded by private and federal sources, and is managed by a team of storied EDA veterans, successful entrepreneurs and internationally renowned researchers.


    The Debugging Problem

    Debugging is one of the most time consuming and resource intensive tasks in the IC design cycle.

    • Debugging accounts for 60% of verification: weeks and months per design
    • Locating and fixing bugs is performed 100% manually
    • Cyclical tasks performed hundred of times per design by many engineers
    • Involves designers, verification engineers, CAD specialists, etc.


    Without OnPoint, engineers have little more than waveform viewers and navigation tools to aid in the manual debugging effort.


    Vennsa OnPoint automates the manual tasks of debug and error localization at the register transfer level (RTL), drastically reducing the time required to locate and correct errors.

    Management

    Dr. Andreas Veneris

    President and CEO

    Andreas Veneris is an international leader in the area of circuit debugging and verification. He has 15 years of R&D experience in debugging with more than 50 publications and five patents in that field. In addition to these credentials, he was an early member at OnRamp Inc., a pioneering internet multimedia company that went public in 1997. While at OnRamp, he was a member of the team that performed the first webcast. He also worked in the early stages of the development of Mosaic (later Netscape) at the National Center for Supercomputing Applications. His operating experience is complemented by extensive experience in team building and technology transfer. As an associate professor at the University of Toronto, he managed a large group of R&D activities and delivered them to the industry with specialized in-house tools. Prior to that, he was a visiting faculty at the University of Illinois, Urbana-Champaign where he also obtained his Ph.D. He holds an M.Sc. degree from the University of Southern California and a Bachelor degree from the University of Patras. He is a senior member of IEEE and co-author of two books.


    Dr. Sean Safarpour

    CTO and VP of Engineering

    Sean Safarpour has extensive industrial and academic experience in hardware and software research and development. Prior to co-founding Vennsa, he held ASIC and FPGA design and verification positions at start-up companies such as Westbay Networks and Vector12 as well as large companies such as Infineon, Altera, and Brooks Automation. Dr. Safarpour is an international expert in the field of design debugging and error localizations with over 20 papers published in the top conferences and journals. He is one of the major contributors to the technical breakthrough in design debugging technology. He obtained the Ph.D. and M.A.Sc. degrees from the University of Toronto and the B.A.Sc. degree from the University of British Columbia.


    Mr. Lavi Lev

    Executive Chairman of Board

    Lavi Lev has more than twenty five years of experience in the semiconductor, EDA and ATE industries at companies including National Semiconductor, Intel, Sun Microsystems, Silicon Graphics, MIPS Technologies Cadence Design Systems and Credence Systems. He most recently served as the President and CEO of Credence Systems, a global provider of semiconductor test equipment. Prior to this role Mr. Lev served as Executive VP and GM at Cadence Design Systems, Inc. where he had responsibility for Cadence's worldwide product portfolio. In his various roles in the semiconductor industry, Mr. Lev has developed microprocessor and system-on-a-chip solutions for supercomputers, workstations, PCs, and consumer devices, including the first Pentium and UltraSparc microprocessors. He is also an author of numerous patents in the field of digital and analog circuit design, CAD techniques, and internet technologies. Mr. Lev holds a Bachelor of Science degree in electrical engineering from Technion, Israel Institute of Technology.


    Mr. Naoto Kimura

    President of Sales, Japan Region

    Naoto Kimura's experience in design automation incorporates over 25 years of R&D, technical support and sales management responsibilities in EDA and in the computer industry. He has four years of R&D experience and six years of FAE for RTL verification experience at Zuken and ZYCAD. Later, he joined Cray research and SGI as a technical consultant with his leading technical knowledge of system design architecture. In the last 10 years, he engaged in sales of static functional verification tools mainly as the president of Averant Japan K.K. and as sales representative of other formal tools in Japan for N.American companies.


    Advisors

    Dr. Masahiro Fujita

    Technical Advisor

    Masahiro Fujita received his Ph.D. degree in Information Engineering from the University of Tokyo in 1985 and shortly after joined Fujitsu Laboratories Ltd. From 1993 to 2000, he had been assigned to Fujitsu's US research office and directed the CAD research and development group. In March 2000, he joined the department of Electronic Engineering in the University of Tokyo as a professor. He is now a professor at VLSI Design and Education Center (VDEC) in the university. He has co-authored 7 books, and has over 150 publications. He has received several awards from Japanese major scientific societies on his works in formal verification and logic synthesis. His Doctoral degree thesis was written in early 80's and on model checking. Since then he has been involved in many research projects on various aspects of formal verification. His current research interests include synthesis and verification in higher level design stages, hardware/software co-designs and also digital/analog co-designs.


    Dr. Magdy S. Abadir

    Technical Advisor

    Magdy S. Abadir received the B.Sc. degree with honors in Computer Science from the University of Alexandria, Egypt in 1978, the M.Sc. degree in Computer Science from the University of Saskatchewan, Saskatoon, Canada, in 1981, and the Ph.D. degree in Electrical Engineering from the University of Southern California (USC), Los Angeles, in 1986. Currently he is the manager for Global Strategy and Operations in the Design Technology Flows and Methodology group, Freescale Semiconductor. He has also been an adjunct faculty at the University of Texas at Austin. He co-founded a series of international workshops on the economics of design, test and manufacturing and on microprocessor test and verification. He has co-edited several books on those subjects, and published over 120 technical journal and conference papers in these areas. Three of his papers received best paper awards and he is a fellow of IEEE.


    Mr. Robert Wood

    Business Advisor

    Rob Wood is a member of the Purple Angel, an angel investment group in Ottawa, Canada and is an advisor to start-up companies on their commercialization and business development strategies. Rob is actively engaged with the Ontario Centres of Excellence and Investment Accelerator Fund. Mr. Wood started his career at Nortel Networks where he spent 33 years. In the last 10 years of his career there, he was a VP responsible for developing and selling a product portfolio specifically for the cable sector and for technical sales of next generation networking products. Rob has an electrical engineering degree from UBC and a Master's in communication engineering from Imperial College, University of London.