- Debugging accounts for 60% of verification: it takes weeks and months per design.
- Failure triage is typically inefficient and inaccurate.
- Locating and fixing bugs is performed manually.
- Repetitive tasks are performed hundreds of times per design by many engineers.
- Involves designers, verification engineers, CAD specialists, etc.
Vennsa Technologies is the leading supplier of automated debugging and error localization software. Leveraging over 15 years of cutting edge research and patented IP, Vennsa's technology has been validated by numerous customers and partners. Vennsa is well funded by private and federal sources, and is managed by a team of storied EDA veterans, successful entrepreneurs and internationally renowned researchers.
The Debugging Problem
Debugging is one of the most time consuming and resource intensive tasks in the IC design cycle.
Without OnPoint, engineers have little more than waveform viewers and navigation tools to aid in the manual debugging effort. Vennsa OnPoint automates the manual tasks of debug and error localization at the register transfer level (RTL), drastically reducing the time required to locate and correct errors.
Dr. Andreas Veneris
President and CEO
Andreas Veneris is an international leader in the area of circuit debugging and verification. He has 15 years of R&D experience in debugging with more than 70 publications and five patents in that field. In addition to these credentials, he was an early member at OnRamp Inc., a pioneering internet multimedia company that went public in 1997. While at OnRamp, he was a member of the team that performed the first webcast, an event acknowledged by the American Congress. He also worked in the early stages of the development of Mosaic (later Netscape) at the National Center for Supercomputing Applications. His operating experience is complemented by extensive experience in team building and technology transfer. As an associate professor at the University of Toronto, he managed a large group of R&D activities and delivered them to the industry with specialized in-house tools. Prior to that, he was a visiting faculty at the University of Illinois, Urbana-Champaign where he also obtained his Ph.D. He holds an M.Sc. degree from the University of Southern California and a Bachelor degree from the University of Patras. He is a senior member of IEEE and co-author of two books.
Mr. Naoto Kimura
President of Sales, Japan Region
Naoto Kimura's experience in design automation incorporates over 25 years of R&D, technical support and sales management responsibilities in EDA and in the computer industry. He has four years of R&D experience and six years of FAE for RTL verification experience at Zuken and ZYCAD. Later, he joined Cray research and SGI as a technical consultant with his leading technical knowledge of system design architecture. In the last 10 years, he engaged in sales of static functional verification tools mainly as the president of Averant Japan K.K. and as sales representative of other formal tools in Japan for N.American companies.
Prof. Res Saleh
Business / Technical Advisor
Res Saleh was a Founder of Simplex Solutions which developed computer-aided design (CAD) software for deep submicrometer digital design verification. Prior to starting Simplex, he spent nine years as a Professor with the Department of Electrical and Computer Engineering, University of Illinois, Urbana. He also taught for one year at Stanford University. He was with Mitel Corporation, Toshiba Corporation, Tektronix and Nortel. He is currently a Professor and was Natural Sciences and Engineering Research Council/PMC Sierra Chairholder from 2000-2010 with the System-on-Chip (SoC) Laboratory, Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, in the field of SoC design and test. He has published over 100 journal articles and conference papers and he coauthored a book. Dr. Saleh received the Presidential Young Investigator Award in 1990 from the National Science Foundation in the U.S. He has served as General Chair, Conference Chair and Technical Program Chair in many IEEE conferences and he has also served as Associate Editor of the IEEE Transactions on CAD. He was inducted into the Canadian Academy of Engineering in 2009. Resve A. Saleh received the B.S. degree in electrical engineering from Carleton University, Ottawa, ON, Canada, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley.
Prof. Masahiro Fujita
Masahiro Fujita received his Ph.D. degree in Information Engineering from the University of Tokyo in 1985 and shortly after joined Fujitsu Laboratories Ltd. From 1993 to 2000, he had been assigned to Fujitsu's US research office and directed the CAD research and development group. In March 2000, he joined the department of Electronic Engineering in the University of Tokyo as a professor. He is now a professor at VLSI Design and Education Center (VDEC) in the university. He has co-authored 7 books, and has over 150 publications. He has received several awards from Japanese major scientific societies on his works in formal verification and logic synthesis. His Doctoral degree thesis was written in early 80's and on model checking. Since then he has been involved in many research projects on various aspects of formal verification. His current research interests include synthesis and verification in higher level design stages, hardware/software co-designs and also digital/analog co-designs.
Mr. Larry Lapides
Larry Lapides is an independent consultant, providing sales and marketing services for startup companies. Larry currently runs sales and marketing at Imperas Software Ltd., and previously ran worldwide sales at EDA companies Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before Verisity and SureFire Verification (acquired by Verisity), Larry held positions in sales and marketing for Exemplar Logic and Mentor Graphics. Larry was recently an Entrepreneur-in-Residence at Clark University's Graduate School of Management, where he developed and taught a course on Entrepreneurial Communication and Influence. Larry holds a BA in Physics from the University of California Berkeley, a MS in Applied and Engineering Physics from Cornell University and a MBA from Clark University. Outside of high tech, Larry enjoys food and wine, and contributes to his wife's website for wine region travel, ViciVino.com.
Prof. C.L. "Dave" Liu
Prof. Liu serves on the the Board of Andes Technology Corporation, Anpec Electronics Corporation, Cadence Methodology Service Company, Delta Networks Incorporated, Dramexchange Corporation, Macronix International Co., Ltd., MediaTek Incorporation, Mototech Technology Corporation, United Microelectronics Corporation, and TCL Communication Technology Holdings Limited. He is a member of Academia Sinica, and a Fellow of IEEE and ACM. He was conferred an Honorary Doctoral Degree at the University of Macau (2004). He received a Life Time Achievement Award from the International Conference on VLSI Design (2005), a Technical Achievement Award from the Real Time Systems Technical Committee, IEEE (1999), a Technical Achievement Award from the Circuits and Systems Society, IEEE (1998), and an Education Medal, IEEE (1994). Dave received his B. Sc. degree at the National Cheng Kung University in1956, and Sc. D. degree at the Massachusetts Institute of Technology in 1962. He is currently the William M. W. Mong Honorary Chair Professor at the National Tsing Hua University where he also served as President from 1998 to 2002. He was a faculty member at the University of Illinois at Urbana-Champaign (1972 -1998), and at the Massachusetts Institute of Technology (1962-1972).
Dr. Magdy S. Abadir
Magdy S. Abadir received the B.Sc. degree with honors in Computer Science from the University of Alexandria, Egypt in 1978, the M.Sc. degree in Computer Science from the University of Saskatchewan, Saskatoon, Canada, in 1981, and the Ph.D. degree in Electrical Engineering from the University of Southern California (USC), Los Angeles, in 1986. Currently he is the manager for Global Strategy and Operations in the Design Technology Flows and Methodology group, Freescale Semiconductor. He has also been an adjunct faculty at the University of Texas at Austin. He co-founded a series of international workshops on the economics of design, test and manufacturing and on microprocessor test and verification. He has co-edited several books on those subjects, and published over 120 technical journal and conference papers in these areas. Three of his papers received best paper awards and he is a fellow of IEEE.