Vennsa OnPoint™

    A Breakthrough in Debug

    Today, engineers have few tools to aid them with their debugging needs. Waveform viewers, visualization tools, navigation aids, and built-in debug features require manual intervention and provide no automation, making debug painstakingly difficult.


    OnPoint goes beyond debug. It offers a significant breakthrough in circuit debugging and error localization. Once verification fails, OnPoint uses proprietary technology to automatically analyze the design and return the root cause of errors. There is no need for manually tracing signals, performing "what if" analysis, and annotating values in the source code. OnPoint performs these task automatically, analyzes the results and returns the error sources to the user. As shown in the table below, it is the only tool offering error source localization thus drastically reducing the debug time.


    Category Vennsa OnPoint Schematic and Waveform Debug tools Simulators and Debugging Environments Formal Verification Tools
    Waveform viewer
    Schematic viewer some some
    Cross-referencing
    Root Cause Analysis
    Pinpoint lines of code
    Categorized Errors
          RTL suspects
          Assertion suspects
          Missing assumptions
    Ranked high priority sources
    Correction hints
    Correction waveforms


    OnPoint complements assertion-based verification (ABV) methodologies and works seamlessly with existing simulation and formal verification tools to automatically locate the source of failure at the register transfer level (RTL) or in assertions and assumptions. It integrates in minutes and only requires about two hours of training.


    OnPoint analyzes the RTL and assertion files of the design along with the failing simulation trace from the verification tool, and produces a set of error suspects and correction waveforms that can fix the bug.


    The OnPoint Advantage

    OnPoint is a root causes analysis tool that identifies the source of errors, or suspects, and categorizes them by:

    • RTL source: lines in the source code of the design
    • Assumptions: under-constrained verification problems
    • Assertions: errors or missing signals in assertions
    Each error source contains:
    • A location in the source code
    • A hint for performing a fix
    • A rank for targeting high priority sources
    • A waveform with correction values
    • A summary of debug information



    Vennsa OnPoint can find any kind of functional bug in the design, assertion, or assumptions. A sample list of errors is shown below.

    • Conceptual or high level errors
    • State transition bugs
    • Bugs in assertions
    • Bugs in assumptions and constraints
    • Incorrect assignments
    • Wrong operations
    • Wrong if/case conditions
    • Problems with module instantiation
    • Bad module wiring
    • and many more...

    Supported Verification Tools

    OnPoint supports the following simulators:

    • Incisive
    • Modelsim
    • Questa
    • VCS

    OnPoint supports the following formal verification tools:

    • 0-In
    • Incisive Formal Verifier
    • JasperGold
    • Magellan
    • Solidify